1. Field of the Invention
This invention relates to transistor devices and more particularly to pull-down transistor structures.
2. Description of Related Art
There is a problem of leakage in the drains of pull down transistors in SRAM circuits. There is no drain offset so there is drain induced lowering of barrier potential .phi..sub.B and band-to-band tunnelling for the pull down transistor limits performance. In particular, a large leakage current is caused in a low power Static Random Access Memory (SRAM) cell, especially in cases in which the thickness of the gate is very thin, (that is .ltoreq. about 150.ANG.) Since an SRAM is designed to retain stored data indefinitely, this is a problem since the leakage will reduce the length of time during which the data can be stored. As the poly resistor and pull down transistor are connected in series, if the pull down leakage current is large relative to the poly resistor, the storage node cannot pull high, so data is lost. If we simply push the poly resistor high (poly resistor resistance is low) then the SRAM cannot operate with low power. Thus, the best solution is to reduce the leakage current of the pull down transistor.